1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices such as LSI, particularly to a semiconductor integrated circuit device which inhibits a capability of a circuit from being degraded by a power voltage drop generated in the circuit disposed in the semiconductor integrated circuit device.
This application is counterpart of Japanese patent application, Serial Number 382455/2003, filed Nov. 12, 2003, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, semiconductor integrated circuit devices such as LSI have been asked to have an enlarged scale or multiple functions, and there has been a tendency to complicate the constitution of the semiconductor integrated circuit device and to increase the circuit area. This has resulted in an increase in resistance by drawing around a power wiring and a ground wiring disposed in the semiconductor integrated circuit device, or in a decrease in a power voltage for the purpose of saving power consumption and increasing the speed of the circuit. This has caused a voltage drop in the supply voltage in circuits disposed in positions distant from a power supply, and has caused problems such as defective operation and a decrease in the operation speed of the circuit.
To solve the problems, a method has been used in which supply portions of the power voltage are increased or the supply portions are devised to decrease circuits to be disposed in positions distant from the supply portions or a meshed or thick power wiring is disposed to reduce an effective wiring resistance.
Moreover, as a device which inhibits the voltage drop of the supply voltage in a general circuit disposed in the position distant from the power supply, a semiconductor integrated circuit device has been known which detects an internal power voltage level and an internal ground voltage level of the general circuit disposed in a semiconductor integrated circuit. In the device, the general circuit is controlled so as to compensate for a change of the voltage level of the general circuit by obtained internal power voltage detection signal and internal ground voltage detection signal (e.g., see Japanese Patent Application Laid-Open No. 05-315544).
However, in the method of increasing the power supply portions, input pads need to be increased in order to secure the power supply portions. In the method of devising the shape of the power wiring or thickening the power wiring, there is a problem that a layout area of a power wiring portion increases. In this method, the effective resistance of the power wiring decreases but is not completely eliminated. Therefore, this method cannot sufficiently cope with the reduced voltage or the enlarged scale, and cannot be said to be an actually useful method.
Moreover, the conventional semiconductor integrated circuit device for inhibiting the voltage drop of the supply voltage in the general circuit disposed in the position distant from the power supply has a problem that a circuit for detecting the internal power voltage level and internal ground voltage level is required for each general circuit. Another problem is that the wiring on the semiconductor integrated circuit device is complicated.